1. Field
Example embodiments relate to a vertical memory device and a method of manufacturing the same, and more particularly, to a vertical NAND flash memory device and/or a method of manufacturing the same.
2. Description of Related Art
A vertical NAND flash memory device in which a plurality of memory cells is vertically stacked on a substrate has been proposed for increasing memory capacity of the NAND memory devices.
As the vertical NAND flash memory device tend to be downsized together with high stack density of the memory cells, the electron diffusion and the cross talk occurs much more frequently between the vertically neighboring stack cells, which affect the reliability of the vertical NAND flash memory device.
For reducing and/or minimizing the electron diffusion and the cross talk between the vertically stack cells, a charge trap pattern is provided as a separate pattern by each cell in the vertical direction.
As the stack density of the memory cells increases in the vertical NAND flash memory devices, the vertical gap distances of the memory cells are shortened and as a result, the height of the charge trap pattern also decreases in the vertical NAND flash memory devices. Accordingly, the trap density in the charge trap pattern is not sufficient each cell of the vertical NAND flash memory device, which makes the memory window size of the flash memory device very variable and unstable in response to the size of the flash memory device.
In addition, the reduction of the vertical gap distance between the neighboring stack cells usually cause the electron diffusion and the cross talk between the neighboring stack cells in the vertical NAND flash memory device.